This invention relates to a pulse generator circuit arrangement which is triggerable to generate an output pulse of minimum duration T by a transition of a signal at an input thereof from a first to a second logic level. The invention also relates to a memory arrangement including such a pulse generator arrangement.
Some known such pulse generator arrangements take the form of retriggerable monostable multivibrators or "one-shots". If these are supplied with a single input pulse an output pulse of duration T (often defined by the time constant of an RC circuit) is produced. If a single further input pulse is supplied to the arrangement white the output pulse is present, the duration of the output pulse is extended so that it now terminates at substantially a time T after the leading edge of the further input pulse. The output pulse can be extended further in an analogous manner if yet further input pulses are supplied to the arrangement input white the output pulse is still present. The known arrangements tend to be rather complicated, and hence occupy a relatively large area of semiconductor surface if they are constructed in integrated circuit form.
In semiconductor memory integrated circuits the data paths are often of the differential type, the data bit carried by such a path at any given time being indicated by the sense of the difference between the potentials on a pair of conductors which together form the path. Prior to the application of a data bit to such a path, for example from an accessed memory cell, it is known to equalise the potentials on the two conductors by temporarily effectively connecting them together, in order to prevent any difference in potential already present from masking the required data bit when it is subsequently impressed on the path. Obviously such equalisation is only required when a new cell is accessed and, to this end, it is known to provide a so-called address transition detector circuit corresponding to each address bit input of the integrated circuit, this detector producing an output pulse each time the corresponding address bit changes, and initiating the equalisation function. The use of such address transition detectors is described, for example, in an article entitled "A 40-ns/100-pF low-Power Full-CMOS 256K (32K.times.8) SRAM" by Gubbels et al. in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pages 741-747. In this known memory the output signals of the address transition detectors are combined by means of a wired-OR and trigger an equalization pulse generator each time a change of address occurs. The resulting pulse from the generator in turn controls the equalization function, inter alia by controlling conduction in a transistor connected between the conductors of the data path. The duration of each pulse can be chosen so that each conduction period is sufficiently long for satisfactory equalization to be obtained, termination thereof allowing data to be impressed on the path. However, it is often the case that address bits do not change simultaneously, but rather in a skewed manner. If the duration of each equalization pulse were fixed then, if this duration were comparatively short, it could be that it would terminate before the address had settled, with the result that data from an incorrect memory location would be liable to be impressed on the path. On the other hand, if this duration were long enough to embrace the worst possible skewing of an address change many memory location accessing operations would take longer than they inherently need. Of course, the equalization pulse generator could take the form of a conventional retriggerable monostable multivibrator but, as pointed out above, these tend to be rather complicated. Moreover, in such a case each equalization pulse would terminate a time T after the last address bit to change has changed, where T has to be sufficiently long for satisfactory equalization to take place even if all the changing address bits were to change simultaneously. This again would be liable to result in many memory accessing operations taking longer than they inherently need.